Phase-locked loop (PLL) circuits accept an input reference signal and generate an output signal that is related in phase and/or frequency to the reference signal. The relationship between the output signal and the reference signal is controlled by a number of configuration parameters that generally include a feedback loop divider value, a choice of voltage controlled oscillators (VCOs), and a tuning value for the selected VCO which specifies a coarse frequency sub-band within the VCOs frequency range. The loop divider is a value that determines a ratio between the output signal frequency and the reference signal frequency for a given combination of reference signal, VCO, and tuning value. The PLL can generally be reconfigured as needed to provide an output signal with desired characteristics by adjusting one or more of these configuration parameters.
Variations in voltage, temperature, and other conditions, can cause the PLL to change behavior over time. For example, the band-edges and/or bias settings of the VCOs can shift, resulting in performance degradation of the PLL. This degradation can include increased acquisition time (i.e., the time for the PLL to lock on to the phase of the reference) and reduced frequency accuracy. Periodic calibration of the PLL can help to overcome these problems.
Existing calibration methods typically attempt to match each possible loop divider value with other appropriate PLL settings necessary to generate each desired output frequency at an acceptable level of fidelity. This approach generally requires a table of configuration parameters that includes an entry for each output frequency step size (e.g., loop divider value). The size of this table can vary greatly, however, for highly-configurable PLLs that employ multiple VCOs, many tuning values, and support a wide range of reference signal frequencies. A general purpose PLL hardware implementation must support the worst-case scenario with the largest possible table size. This approach is inefficient, both in memory consumption and table search processing, for PLL applications that operate over smaller frequency ranges that are associated with smaller subsets of the largest table size.
Although the following Detailed Description will proceed with reference being made to illustrative embodiments, many alternatives, modifications, and variations thereof will be apparent to those skilled in the art.